A semiconductor device includes a delay locked loop (DLL) circuit configured to generate an internal clock signal which is a signal obtained by delaying an externally input external clock signal by an amount of time in accordance with specifications, and to output the internal signal to other circuits. An example of a DLL circuit is a master/slave DLL circuit.
A master/slave DLL circuit includes a master DLL circuit and a slave DLL circuit. The master DLL circuit generates delay control values for delaying the phase of an externally input reference clock signal from 0° to 360°, for example, and thereby detects a delay control value (lock delay control signal) obtained when the reference clock signal is delayed by a phase of approximately 360°. The slave DLL circuit delays an externally input external clock signal by a desired phase based on the detected lock delay control value and a phase setting value provided from an external apparatus.
In the DLL circuit, the slave DLL circuit delays an external clock signal by a desired phase based on the lock delay control value generated by the master DLL circuit and outputs the delayed signal as an internal clock signal.
A DLL circuit may be used in, for example, a double-data-rate synchronous dynamic random access memory (DDR-SDRAM) interface. The DLL circuit generates an internal signal delayed by approximately 90° with respect to an external clock signal.
A DDR-SDRAM, which allows data transfer in synchronization with both the rising edge and falling edge of an external clock signal, realizes a throughput which is twice the throughput of a typical SDRAM. In accordance with the DDR-SDRAM specifications, the transmission and reception timings of a data signal are controlled using a data strobe signal.
The phases of the data strobe signal and data signal are adjusted respectively at the time of data transmission (write) from an interface circuit to a DDR-SDRAM and at the time of data reception (read) in the interface circuit so that the transmission and reception timings of a data signal are controlled.
In the writing operation, the data strobe signal and data signal are generated respectively at the rising edge and falling edge of an external clock signal, and the DLL circuit delays the data strobe signal by a phase of approximately 90°. The data strobe signal and data signal are transmitted to the DDR-SDRAM through the interface circuit.
In the reading operation, since the data strobe signal and data signal received from the DDR-SDRAM via the interface circuit are synchronized at substantially the same timings, the DLL circuit delays the data strobe signal by a phase of approximately 90° and the received data signal is read in synchronization with the data strobe signal delayed by approximately 90°.
The master DLL circuit includes a first delay circuit, a phase comparator circuit, and a delay control circuit.
The first delay circuit generates a delayed reference clock signal by delaying the phase of a reference clock signal received from an external apparatus in accordance with a delay control value supplied from the delay control circuit. The phase comparator circuit receives the reference clock signal and the delayed reference clock signal from the first delay circuit. The phase comparator circuit detects the phase difference between the delayed reference clock signal and the reference clock signal, and outputs the detection result to the delay control circuit as a phase difference value.
The delay control circuit, based on the phase difference value from the phase comparator circuit, generates delay control values which cause the first delay circuit to delay the phase of the reference clock signal, for example, from 0° to 360°. When the delayed reference clock signal is delayed by a phase of approximately 360° with respect to the reference clock signal and enters a substantially synchronized (locked) state, the delay control circuit holds the delay control value (lock delay control value).
The slave DLL circuit includes a second delay circuit and a phase adjustment circuit.
The second delay circuit generates an internal clock signal that is obtained by delaying the phase of an external clock signal received from an external apparatus in accordance with a phase adjustment value. The phase adjustment circuit receives the lock delay control value received from the master DLL circuit and phase setting data received from the external apparatus. The phase adjustment circuit, based on the lock delay control value and the phase setting value data, generates a phase adjustment value that causes the phase of the external clock signal to be delayed to reach a desired phase through the second delay circuit, whereby the internal clock signal is generated. The phase adjustment circuit outputs the phase adjustment value to the second delay circuit.
A plurality of slave DLL circuits are provided for each master DLL circuit in a semiconductor device. Since wire delay times generated by wires from the slave DLL circuit to respective circuits arranged in the semiconductor device are averaged, the variations among the internal clock signals input to the circuits arranged in the semiconductor device may be decreased.
In recent years, in accordance with an increase in clock signal speeds, there have been efforts to reduce the phase variations among internal clock signals input to circuits arranged in a semiconductor device.
When a plurality of slave DLL circuits are arranged in a semiconductor device, as described above, processing variations may cause the slave DLL circuits to delay phases by different amounts even when the same phase adjustment value is input.
Processing variations among the second delay circuits of the slave DLL circuits may be corrected by feeding back internal clock signals generated by the slave DLL circuits to the phase comparator circuit of the master DLL circuit, and thereby comparing, in the phase comparator circuit, the fed back internal clock signals and the external clock signal whose phase has been delayed by the first delay circuit (for example, JP2005-142859).
However, the DLL circuit described above fails to address the wiring delay caused by a wire between the first delay circuit and phase comparator circuit of the master DLL circuit, and the delay times caused by the input buffer circuits and output buffer circuits provided in the second delay circuits within the slave DLL circuits. Hence, the DLL circuit described above may fail to delay the phase of an internal clock signal by a desired value.